1. Field of the Invention
The present application relates to methods and circuitry for processing clock signals.
2. Discussion of the Related Art
Clock signals are typically used in electrical circuits to regulate the timing of the operations of the circuit. A clock signal has periodic transitions (at least one of rising or falling edges) which are spaced apart by the same interval, such that operations can be carried out in the circuit in accordance with the timing of the transitions of the clock signal.
Double edge clocking is a technique for speeding up switching in logic circuits. The circuit shown in FIG. 1 is one example of a circuit 100 that uses both edges of a clock signal (both falling and rising edges) to trigger the circuit.
Circuit 100 comprises two DQ flip-flops 101 and flip-flop 102 wherein the output Q of flip-flop 101 is connected to the data input D of flip-flop 102 via a combinatory logic block 104. The block 104 represents logic for processing the Q outputs of the flip flop 101 before applying it to the D input of flip flop 102.
The DQ flip-flops 101, 102 each have a clock input CP which is activated on a rising edge. When the clock signal has a rising edge, the rising edge presented at the CP input of flip-flop 102 will activate it. The clock signal is also input to inverter 103 which inverts the clock signal so that a falling edge is input into the CP input of the flip-flop 101, failing to activate it. When the clock signal has a falling edge, it is inverted by inverter 103 so that a rising edge activates the CP input of the flip-flop 101.
Using both edges of a clock signal (both falling and rising edges) to trigger a circuit can be problematic. The interval between the rising and falling edges is constant, but the delay created by the inverter 103 applied to the clock signal can cause the “inverted” rising edge to be delayed, causing triggering differences which for example can lead to a reduced margin in the circuit being triggered.